CpcAlive is a programming
environment Amstrad CPC
compatible.

Cpc basic key words
( English - Español )
Cpc basic error messages
The memory
The Cpc system vectors
Diskettes management
Z80 processor opcodes and
operation
CpcAlive installer for Windows 95
to Windows 7 (V1.09M)
and for DosBox
CpcAlive Documentation
SmallAsm is a Z80 assembler
for Dos or Windows console
     
Z80 opcodes and operation
       
Web documents:
Introduction to Z80 assembler
Z80 Map

ADC A,S , ADC HL,RR , ADD A,(HL) , ADD A,(IX+d) , ADD A,(IY+d) , ADD A,N , ADD A,R
ADD HL,RR , ADD IX,RR , ADD IY,RR , AND S
 BIT b,(HL) , BIT b,(IX+d) , BIT b,(IY+d) , BIT b,R
CALL cond NN , CALL NN , CCF , CP S , CPD , CPDR , CPI , CPIR , CPL
DAA , DEC M , DEC RR , DEC IX , DEC IY , DI , DJNZ e
EI , EX AF,AF' , EX DE,HL , EX (SP),HL , EX (SP),IY , EXX
HALT
IM 0 , IM 1 , IM 2 , IN R,(C) , INC M , INC RR , INC IX , INC IY , IND , INDR , INI , INIR
JP cond NN , JP NN , JP (HL) , JP (IX) , JP (IY) , JR cond e , JR e
LD RR,(NN) , LD RR,NN , LD R,N , LD R,R' , LD (BC),A , LD (HL),N , LD (HL),R , LD R,(IX+d) , LD_R,(IY+d) , LD (IX+d),N
LD (IY+d),N , LD (IX+d),R , LD (IY+d),R , LD (NN),A , LD (NN),RR , LD (NN),IX , LD (NN),IY , LD A,(BC)
LD A,(DE) , LD A,I , LD I,A , LD A,R , LD HL,(NN) , LD IX,NN , LD IX,(NN) , LD IY,NN , LD IY,(NN) , LD_R,(HL)
LD R,A , LD SP,HL , LD SP,IX , LD SP,IY , LDD , LDDR , LDI , LDIR
NEG , NOP
OR S , OTDR , OTIR , OUT (C),R , OUT (N),A , OUTD , OUTI
POP RR , POP IX , POP IY , PUSH RR , PUSH IX , PUSH IY
RES b,S , RET , RET cond , RETI , RETN , RL S , RLA , RLC S , RLCA , RLD , RR S , RRA , RRC S , RRCA , RRD , RST N
SBC A,S , SBC HL,RR , SCF , SET b,S , SLA S , SRA S , SRL S , SUB A,S
XOR S

ADC A,S Add with carry operand S to register A
S can be:
- registers A,B,C,D,E,H or L
- an immediate value N -> ex: ADC A,9
- a memory adress pointed by HL -> ex: ADC A,(HL)
- a memory adress pointed by IX+d -> ex: ADC A,(IX+10)
- a memory adress pointed by IY+d -> ex: ADC A,(IY+4)
Flags:
S Z - H - P/V N C
0



ADC HL,RR Add with carry register pair RR to HL
RR can be BC, DE, HL or SP.
Flags:
S Z - H - P/V N C
? 0
H is set if the bit 11 is reported.


ADD A,(HL) Add location (HL) to register A
Flags:
S Z - H - P/V N C
0



ADD A,(IX+d) Add location (IX+d) to register A
Flags:
S Z - H - P/V N C
0



ADD A,(IY+d) Add location (IY+d) to register A
Flags:
S Z - H - P/V N C
0



ADD A,N Add value n to register A
Flags:
S Z - H - P/V N C
0



ADD A,R Add register R to register A
R can be A,B,C,D,E,H,L
Flags:
S Z - H - P/V N C
0



ADD HL,RR Add register pair RR to HL
RR can be BC, DE, HL or SP.
Flags:
S Z - H - P/V N C


?
0
C is set if the bit 15 is reported, cleared if not.
H is set if the bit 11 is reported.



ADD IX,RR Add register pair RR to IX
RR can be BC, DE, IX or SP.
Flags:
S Z - H - P/V N C


?
0
C is set if the bit 15 is reported, cleared if not.
H is set if the bit 11 is reported.



ADD IY,RR Add register pair RR to IY
RR can be BC, DE, IY or SP.
Flags:
S Z - H - P/V N C


?
0
C is set if the bit 15 is reported, cleared if not.
H is set if the bit 11 is reported.



AND S Logical AND of operand S to register A
S can be:
- one of registers A,B,C,D,E,H or L
- an immediat value N -> ex: AND 9
- a memory adress pointed by HL -> ex: AND (HL)
- a memory adress pointed by IX+d -> ex: AND (IX+10)
- a memory adress pointed by IY+d -> ex: AND (IY+4)
Flags:
S Z - H - P/V N C
1 0 0



BIT b,(HL) Test bit b of location (HL)
Flags:
S Z - H - P/V N C
? 1 ? 0



BIT b,(IX+d) Test bit b of location (IX+d)
Flags:
S Z - H - P/V N C
? 1 ? 0



BIT b,(IY+d) Test bit b of location (IY+d)
Flags:
S Z - H - P/V N C
? 1 ? 0



BIT b,R Test bit b of register R.
R can be A,B,C,D,E,H,L
Flags:
S Z - H - P/V N C
? 1 ? 0



CALL cond,NN Call subroutine at location NN if condition cond is true
cond can be:
NZ: flag Z=0
Z: flag Z=1
NC: flag C=0
C: flag C=1
PO: flag P/V=0
PE: flag P/V=1
P: flag S=0
M: flag S=1
Flags: no effect
S Z - H - P/V N C



CALL NN Call subroutine at location NN
Flags: no effect
S Z - H - P/V N C



CCF Complement carry flag.
Flags:
S Z - H - P/V N C
? 0



CP S Compare operand S with register A.
The operand S is subtract of register A and result is not keep.
S can be:
- one of registers A,B,C,D,E,H or L
- an immediat value N -> ex: CP 9
- a memory adress pointed by HL -> ex: CP (HL)
- a memory adress pointed by IX+d -> ex: CP (IX+10)
- a memory adress pointed by IY+d -> ex: CP (IY+4)
Flags:
S Z - H - P/V N C
1



CPD Comparison with decrementation
Compare location (HL) with register A and decrement HL and BC.
Flags:
S Z - H - P/V N C
X X 1
The flag Z is set if A=(HL)
The flag P/V is cleared if BC=0 after execution, set if not.



CPDR Bloc comparison with decrementation
Compare location (HL) with register A and decrement HL and BC.
Repeat until BC=0 or A=(HL)
Flags:
S Z - H - P/V N C
X X 1
The flag Z is set if A=(HL)
The flag P/V is cleared if BC=0 after execution, set if not.



CPI Comparison with incrementing
Compare location (HL) with register A. After increment HL and decrement BC.
Flags:
S Z - H - P/V N C
X X 1
The flag Z is set if A=(HL)
The flag P/V is cleared if BC=0 after execution, set if not.



CPIR Bloc comparison with incrementation
Compare location (HL) with register A. After increment HL and decrement BC.
Repeat until BC=0 or A=(HL)
Flags:
S Z - H - P/V N C
X X 1
The flag Z is set if A=(HL)
The flag P/V is cleared if BC=0 after execution, set if not.



CPL Complement register A (1's complement).
Flags:
S Z - H - P/V N C
1 1



DAA Decimal adjust of register A
According to the flags, this instruction conditionally adds 6 to the four-bit byte high and/or low of the register A, for conversion DCB after arithmetics operations.
N C High
four-bit byte
value
 H Low
four-bit byte
value		 #
added
to A		 Carry
after
execution
0
(ADD,
ADC,
INC)		 0
0
0
0
0
0
1
1
1		 0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3		 0
0
1
0
0
1
0
0
1		 0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3		 00
06
06
60
66
66
60
66
66		 0
0
0
1
1
1
1
1
1
1
(SUB,
SBC,
DEC,
NEG)		 0
0
1
1		 0-9
0-8
7-F
6-F		 0
1
0
1		 0-9
6-F
0-9
6-F		 00
FA
A0
9A		 0
0
1
1
Flags:
S Z - H - P/V N C



DEC M Decrement operand M
M can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: DEC (HL)
- a memory adress pointed by IX+d -> ex: DEC (IX+10)
- a memory adress pointed by IY+d -> ex: DEC (IY+4)
Flags:
S Z - H - P/V N C
1



DEC RR Decrement register pair RR
RR can be registers BC, DE, HL or SP.
Flags: no effect
S Z - H - P/V N C



DEC IX Decrement register pair IX
Flags: no effect
S Z - H - P/V N C



DEC IY Decrement register pair IY
Flags: no effect
S Z - H - P/V N C



DI Disable maskable interrupts
Flags: no effect
S Z - H - P/V N C




DJNZ e Decrement B and jump relative if B<>0
The register B is decremented. In the event of null result, the jump is not done. The value of the jump is from -126 bytes to +129 bytes. The assembler calculates the e value automatically if one uses an absolut memory address.
 Flags: no effect
S Z - H - P/V N C



EI Enable maskable interrupts
Enable maskable interrupts after the execution of the instruction wich follow EI.
Flags: no effect
S Z - H - P/V N C



EX AF,AF' Exchange the contents of AF and AF'



EX DE,HL Exchange the contents of DE and HL
Flags: no effect
S Z - H - P/V N C



EX (SP),HL Exchange the location (SP) and HL
Flags: no effect
S Z - H - P/V N C



EX (SP),IX Exchange the location (SP) and IX
Flags: no effect
S Z - H - P/V N C



EX (SP),IY Exchange the location (SP) and IY
Flags: no effect
S Z - H - P/V N C



EXX Exchange the contents of BC,DE,HL with BC',DE',HL'
Flags:no effect
S Z - H - P/V N C



HALT Halt computer and wait for interrupt
Waits until has to receive a signal of interruption or rebootstrapping.
Flags:no effect
S Z - H - P/V N C



IM 0 Set interrupt mode 0
The element which stops must place an instruction to be executed on the data bus. (Unused mode on Amstrad cpc)
Flags:no effect
S Z - H - P/V N C



IM 1 Set interrupt mode 1
An instruction RST 038H is executed when a maskable interruption come.
Flags:no effect
S Z - H - P/V N C



IM 2 Set interrupt mode 2
The element which stops must place a data byte which is used as  low part of an address memory (random value on Amstrad Cpc except Cpc+), the high part of this address provided from register I.
Flags:no effect
S Z - H - P/V N C



IN R,(C) Load the register R with input from device (C)
The peripheral addressed by the register C (B for Amstrad Cpc) is read and the result is loaded in register R.
R can be A,B,C,D,E,H,L
Flags:
S Z - H - P/V N C
0



IN A,(N) Load the register A with input from device N
The peripheral addressed by the immediat value N is read and the result is loaded in register A. (Unfunctional code on Amstrad Cpc)
Flags: no effect
S Z - H - P/V N C



INC M Increment the operand M
M can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: INC (HL)
- a memory adress pointed by IX+d -> ex: INC (IX+10)
- a memory adress pointed by IY+d -> ex: INC (IY+4)
Flags:
S Z - H - P/V N C
0



INC RR Increment register pair RR
RR can be registers BC, DE, HL or SP.
Flags: no effect
S Z - H - P/V N C



INC IX Increment register pair IX
Flags: no effect
S Z - H - P/V N C



INC IY Increment register pair IY
Flags: no effect
S Z - H - P/V N C



IND Input with decrementation
The peripheral addressed by the register C (B for Amstrad Cpc) is read and the result is loaded in the memory addressed by the register pair HL. The register B and the register pair HL are then decremented.
Flags:
S Z - H - P/V N C
? X ? ? 1
Z flag is set if B=0 after instruction, clear else.


INDR Bloc input with decrementation
The peripheral addressed by the register C (B for Amstrad Cpc) is read and the result is loaded in the memory addressed by the register pair HL. The register B and the register pair HL are then decremented. If the register B is not to zero, the instruction counter is decremented of 2 and the instruction is re-executed.
Flags:
S Z - H - P/V N C
? X ? ? 1



INI Input with incrementation
The peripheral addressed by the register C (B for Amstrad Cpc) is read and the result is loaded in the memory addressed by the register pair HL. The register B is decremented and the register pair HL is incremented.
Flags:
S Z - H - P/V N C
? X ? ? 1
Z flag is set if B=0 after instruction, clear else.



INIR Bloc comparison with incrementation
The peripheral addressed by the register C (B for Amstrad Cpc) is read and the result is loaded in the memory addressed by the register pair HL. The register B is decremented and the register pair HL is incremented. If the register B is not to zero, the instruction counter is decremented of 2 and the instruction is re-executed.
Flags:
S Z - H - P/V N C
? X ? ? 1



JP cond,NN Jump to location NN if condition cond is true
cond can be:
NZ: flag Z=0
Z: flag Z=1
NC: flag C=0
C: flag C=1
PO: flag P/V=0
PE: flag P/V=1
P: flag S=0
M: flag S=1
Flags: no effect
S Z - H - P/V N C



JP NN Unconditional jump to location NN
Flags: no effect
S Z - H - P/V N C



JP (HL) Unconditional jump to location (HL)
Flags: no effect
S Z - H - P/V N C



JP (IX) Unconditional jump to location (IX)
Flags: no effect
S Z - H - P/V N C



JP (IY) Unconditional jump to location (IY)
Flags: no effect
S Z - H - P/V N C



JR cond,e Jump relative if condition cond is true
The value of the jump is from -126 bytes to +129 bytes. The assembler calculates the e value automatically if one uses an absolut memory address.
cond can be:
NZ: flag Z=0
Z: flag Z=1
NC: flag C=0
C: flag C=1
Flags: no effect
S Z - H - P/V N C



JR e Unconditional jump relative
The value of the jump is from -126 bytes to +129 bytes. The assembler calculates the e value automatically if one uses an absolut memory address.
Flags: no effect
S Z - H - P/V N C



LD RR,(NN) Load register pair RR with location (NN)
RR can be registers BC, DE, HL or SP.
Flags: no effect
S Z - H - P/V N C



LD RR,NN Load register pair RR with NN   
RR can be registers BC, DE, HL or SP.
Flags: no effect
S Z - H - P/V N C



LD R,N Load register R with value N
R can be A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD R,R' Load register R with register R'
R and R' can are registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD (BC),A Load location (BC) with register A
Flags: no effect
S Z - H - P/V N C



LD (HL),N Load location (HL) with N
Flags: no effect
S Z - H - P/V N C



LD (HL),R Load location (HL) with register R
R can be A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD R,(IX+d) Load register R with location (IX+d)
R can be registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD R,(IY+d) Load register R with location (IY+d)
R can be registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD (IX+d),N Load location (IX+d) with N
Flags: no effect
S Z - H - P/V N C



LD (IY+d),N Load location (IY+d) with N
Flags: no effect
S Z - H - P/V N C



LD (IX+d),R Load location (IX+d) with register R
R can be registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD (IY+d),R Load location (IY+d) with register R
R can be registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD A,(NN) Load register A with location (NN)
Flags: no effect
S Z - H - P/V N C



LD (NN),A Load location (NN) with register A
Flags: no effect
S Z - H - P/V N C



LD (NN),RR Load location (NN) with register pair RR
RR can be registers BC, DE, HL or SP.
Flags: no effect
S Z - H - P/V N C



LD (NN),IX Load location (NN) with register pair IX
Flags: no effect
S Z - H - P/V N C



LD (NN),IY Load location (NN) with register pair IY
Flags: no effect
S Z - H - P/V N C



LD A,(BC) Load register A with location (BC)
Flags: no effect
S Z - H - P/V N C



LD A,(DE) Load register A with location (DE)
Flags: no effect
S Z - H - P/V N C



LD A,I Load register A with register I
Flags:
S Z - H - P/V N C
0 X 0
P/V is put to the IFF2 value


LD I,A Load register I with register A
Flags: no effect
S Z - H - P/V N C



LD A,R Load register A with register R
Flags:
S Z - H - P/V N C
0 X 0
P/V is put to the IFF2 value


LD HL,(NN) Load register pair HL with location (NN)
Flags: no effect
S Z - H - P/V N C



LD IX,NN Load register pair IX with value NN
Flags: no effect
S Z - H - P/V N C



LD IX,(NN) Load register pair IX with location (NN)
Flags: no effect
S Z - H - P/V N C




LD IY,NN Load register pair IY with value NN
Flags: no effect
S Z - H - P/V N C




LD IY,(NN) Load register pair IY with location (NN)
Flags: no effect
S Z - H - P/V N C



LD R,(HL) Load register R with location (HL)
R can be registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



LD R,A Load register R with register A
Flags: no effect
S Z - H - P/V N C



LD SP,HL Load register pair SP with register pair HL
Flags: no effect
S Z - H - P/V N C



LD SP,IX Load register pair SP with register pair IX
Flags: no effect
S Z - H - P/V N C



LD SP,IY Load register pair SP with register pair IY
Flags: no effect
S Z - H - P/V N C



LDD Load location (DE) with location (HL), decrement DE,HL,BC
The memory adressed by HL is loaded in the memory adressed by DE. Then BC, DE and HL are decremented.
Flags:
S Z - H - P/V N C
0 X 0
P/V is cleared if BC=0 after execution, set else.



LDDR Perform an LDD and repeat until BC=0
The memory adressed by HL is loaded in the memory adressed by DE. Then BC, DE and HL are decremented. If BC is not to zero, the instruction counter is decremented of 2 and the instruction is re-executed.
Flags:
S Z - H - P/V N C
0 0 0



LDI Load location (DE) with location (HL), incr DE,HL and decr BC
The memory adressed by HL is loaded in the memory adressed by DE. Then DE and HL are incremented and BC is decremented.
Flags:
S Z - H - P/V N C
0 X 0
P/V is cleared if BC=0 after execution, set else.


LDIR Perform an LDI and repeat until BC=0
The memory adressed by HL is loaded in the memory adressed by DE. Then DE and HL are incremented and BC is decremented. If BC is not to zero, the instruction counter is decremented of 2 and the instruction is re-executed.
Flags:
S Z - H - P/V N C
0 0 0



NEG Negate register A (2's complement)
The contents of the register A is subtract from zero and the result is loaded again in register A.
Flags:
S Z - H - P/V N C
1
C is set if the register A was not to zero before the execution of the instruction.
P will be set if  the register A value was 080h.


NOP No operation
Do nothing.
Flags: no effect
S Z - H - P/V N C



OR S Logical OR of operand S and register A
S can be:
- one of registers A,B,C,D,E,H or L
- an immediat value N -> ex: OR 9
- a memory adress pointed by HL -> ex: OR (HL)
- a memory adress pointed by IX+d -> ex: OR (IX+10)
- a memory adress pointed by IY+d -> ex: OR (IY+4)
Flags:
S Z - H - P/V N C
0 0 0



OTDR Bloc output with decrementation
The memory adress pointed by HL is write on the output port adressed by the register C (B for Amstrad Cpc). Then registers B and HL are decremented and the instruction is re-executed while BC<>0.
Flags:
S Z - H - P/V N C
? 1 ? ? 1



OTIR Bloc output with incrementation
The memory adress pointed by HL is write on the output port adressed by the register C (B for Amstrad Cpc). Then the register B is decremented, the register pair HL is incremented and the instruction is re-executed while BC<>0.
Flags:
S Z - H - P/V N C
? 1 ? ? 1



OUT (C),R Load output port (C) with register R
The register R is write on the output port adressed by the register C. (B for Amstrad Cpc)
R can be registers A,B,C,D,E,H,L
Flags: no effect
S Z - H - P/V N C



OUT (N),A Load output port (N) with register A
The register A is write on the output port adressed by the value N. (Unfunctional code on Amstrad Cpc)
Flags: no effect
S Z - H - P/V N C




OUTD Output with decrementation
The memory adress pointed by HL is write on the output port adressed by the register C (B for Amstrad Cpc). Then registers B and HL are decremented.
Flags:
S Z - H - P/V N C
? X ? ? 1
Z is set if B=0 after execution, clear else.


OUTI Output with incrementation
The memory adress pointed by HL is write on the output port adressed by the register C (B for Amstrad Cpc). Then the register B is decremented and the register pair HL is incremented.
Flags:
S Z - H - P/V N C
? X ? ? 1
Z is set if B=0 after execution, clear else.



POP RR Load register pair RR with top of stack
RR can be registers BC, DE, HL or AF.
Flags: no effect
S Z - H - P/V N C



POP IX Load IX with top of stack
Flags: no effect
S Z - H - P/V N C




POP IY Load IY with top of stack
Flags: no effect
S Z - H - P/V N C



PUSH RR Load register pair RR onto stack
RR can be registers BC, DE, HL or AF.
Flags: no effect
S Z - H - P/V N C



PUSH IX Load register pair IX onto stack
Flags: no effect
S Z - H - P/V N C



PUSH IY Load register pair IY onto stack
Flags: no effect
S Z - H - P/V N C



RES b,S Reset bit b of operand S
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: RES 7,(HL)
- a memory adress pointed by IX+d -> ex: RES 7,(IX+10)
- a memory adress pointed by IY+d -> ex: RES 7,(IY+4)
Flags: no effect
S Z - H - P/V N C



RET Return from subroutine
Flags: no effect
S Z - H - P/V N C




RET cond Return from subroutine if condition  is true
cond can be:
NZ: flag Z=0
Z: flag Z=1
NC: flag C=0
C: flag C=1
PO: flag P/V=0
PE: flag P/V=1
P: flag S=0
M: flag S=1
Flags: no effect
S Z - H - P/V N C




RETI Return from interrupt
An EI instruction must be executed before RETI to enable interruptions.
Flags: no effect
S Z - H - P/V N C



RETN Return from non-maskable interrupt
(The IFF2 contents (safeguard flag) is recopied in IFF1 to restore the state of the interruptions authorization flag before the nonmaskable interruption).
Flags: no effect
S Z - H - P/V N C



RL S Rotate left operand S through carry
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: RL (HL)
- a memory adress pointed by IX+d -> ex: RL (IX+10)
- a memory adress pointed by IY+d -> ex: RL (IY+4)
Flags:
S Z - H - P/V N C
0
 0


RLA Rotate left register A through carry
Flags:
S Z - H - P/V N C
0 0



RLC S Rotate left circular operand S
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: RLC (HL)
- a memory adress pointed by IX+d -> ex: RLC (IX+10)
- a memory adress pointed by IY+d -> ex: RLC (IY+4)
Flags:
S Z - H - P/V N C
0 0



RLCA Rotate left circular register A
Flags: 
S Z - H - P/V N C
0 0



RLD Rotate digit left and right between register A and (HL)
4 lowers bits of (HL) are placed in the highers bits of (HL). The 4 highers bits of (HL) are placed in the 4 lowers bits of register A. The 4 lowers bits  of the register A are placed in the 4 lowers bits of (HL). All these operations occur simultaneously.
Flags:
S Z - H - P/V N C
0 0




RR S Rotate right through carry operand S
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: RR (HL)
- a memory adress pointed by IX+d -> ex: RR (IX+10)
- a memory adress pointed by IY+d -> ex: RR (IY+4)
Flags:
S Z - H - P/V N C
0 0



RRA Rotate right register A through carry
Flags:
S Z - H - P/V N C
0 0



RRC S Rotate operand S right circular
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: RRC (HL)
- a memory adress pointed by IX+d -> ex: RRC (IX+10)
- a memory adress pointed by IY+d -> ex: RRC (IY+4)
Flags:
S Z - H - P/V N C
0 0



RRCA Rotate right circular register A
Flags:
S Z - H - P/V N C
0 0



RRD Rotate digit right and left between register A and (HL)
4 highers bits of (HL) are placed in the lowers bits of (HL). The 4 lowers bits of (HL) are placed in the 4 lowers bits of register A. The 4 lowers bits  of the register A are placed in the 4 highers bits of (HL). All these operations occur simultaneously.
Flags:
S Z - H - P/V N C
0 0



RST  N Call memory adress N
N can be 000H, 008H, 010H, 018H, 020H, 028H,030H,038H
Flags: no effect
S Z - H - P/V N C



SBC A,S Subtract operand S from register A with carry
S can be:
- one of registers A,B,C,D,E,H or L
- an immediat value N -> ex: SBC A,9
- a memory adress pointed by HL -> ex: SBC A,(HL)
- a memory adress pointed by IX+d -> ex: SBC A,(IX+10)
- a memory adress pointed by IY+d -> ex: SBC A,(IY+4)
Flags:
S Z - H - P/V N C
1



SBC HL,RR Subtract register pair RR from HL with carry
RR can be registers BC, DE, HL or SP.
Flags:
S Z - H - P/V N C
? 1
H is set if bit 12 is reported


SCF Set carry flag (C=1)
Flags:
S Z - H - P/V N C
0 0 1



SET  b,S Set bit b of operand S
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: SET 7,(HL)
- a memory adress pointed by IX+d -> ex: SET 7,(IX+10)
- a memory adress pointed by IY+d -> ex: SET 7,(IY+4)
Flags: no effect
S Z - H - P/V N C




SLA S Shift operand S left arithmetic
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: SLA (HL)
- a memory adress pointed by IX+d -> ex: SLA (IX+10)
- a memory adress pointed by IY+d -> ex: SLA (IY+4)
Flags:
S Z - H - P/V N C
0 0



SRA S Shift operand S right arithmetic
The bit 7 keep the same value and the bit 0 go to the carry flag.
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: SRA (HL)
- a memory adress pointed by IX+d -> ex: SRA (IX+10)
- a memory adress pointed by IY+d -> ex: SRA (IY+4)
Flags:
S Z - H - P/V N C
0 0



SRL S Shift operand S right logical
The bit 7 is reset and the bit 0 go to the carry flag.
S can be:
- one of registers A,B,C,D,E,H or L
- a memory adress pointed by HL -> ex: SRL (HL)
- a memory adress pointed by IX+d -> ex: SRL (IX+10)
- a memory adress pointed by IY+d -> ex: SRL (IY+4)
Flags: no effect
S Z - H - P/V N C
0 0



SUB A,S Subtract operand S from register A
S can be:
- one of registers A,B,C,D,E,H or L
- an immediat value N -> ex: SUB A, 9
- a memory adress pointed by HL -> ex: SUB A,(HL)
- a memory adress pointed by IX+d -> ex: SUB A,(IX+10)
- a memory adress pointed by IY+d -> ex: SUB A,(IY+4)
Flags:
S Z - H - P/V N C
1



XOR S Exclusive OR operand S and register A
S can be:
- one of registers A,B,C,D,E,H or L
- an immediat value N -> ex: XOR 9
- a memory adress pointed by HL -> ex: XOR (HL)
- a memory adress pointed by IX+d -> ex: XOR (IX+10)
- a memory adress pointed by IY+d -> ex: XOR (IY+4)
Flags: no effect
S Z - H - P/V N C
0 0 0



Flags:

S Z - H - P/V N C
7 6 5 4 3 2 1 0

C: Carry
N: Add/Subtract
P/V: Parity/Overflow
H: Half Carry
Z: Zero
S: Sign

Value determined by the operation
0 The flag is reset
1 The flag is set
? Random value
X Special case